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FPSC - Field Programmable Systems on Chip

Lattice Semiconductor pioneered the approach of putting ASIC macrocells and FPGA gates on the same silicon die. We call this a Field Programmable System Chip (FPSC). In contrast to ASICs with embedded FPGA gates, FPSCs have a broad range of uses. The embedded macrocells hold industry-standard Intellectual Property - bus interface, high-speed line interface, and high-speed transceivers cores. When these macrocells are combined with hundreds of thousands of programmable gates they can be used in a variety of advanced system designs.

ORLI10G - is a high-speed programmable device for 10Gbits/s data solutions.

ORSO82G5 - includes 8 backplane transceiver channels, each operating at up to 2.7 Gbits/s data rate, providing a full-duplex synchronous interface with built-in Clock/Data Recovery (CDR) and more than 400k usable FPGA system gates.

ORT82G5/42G5 - includes of  8 backplane transceivers, each operating over a range from 600 Mbits/s to 3.7 Gbits/s, with a full duplex synchronous interface with built-in Clock and Data Recovery (CDR), along with more than 400K FPGA system gates

ORT8860H/L - is available in medium and high density versions. Both feature 8 x 850Mbits/s high-speed interfaces. Tthe ORT8850L offers up to 397K FPGA System gates and 278 user I/Os. The ORT8850H offers up to 899K FPGA System gates and 297 user I/Os.

FPGA - Field Programmable Gate Array 

The ispXPGA family of devices allows the creation of high-performance logic designs that are both non-volatile and infinitely reconfigurable. 

ORCA Field Programmable Gate Arrays (FPGAs) by Lattice Semiconductor are a new family of Field Programmable Gate Arrays (FPGAs) built on the familiar Optimized Reconfigurable Cell Array (ORCA) achitecture. 

ispXPGA - Non-Volatile, Infinitely Reconfigurable 
- Power-up in 200usec via On-Chip E² Cells. 
- No External Configuration Memory Needed. 
- 139K to 1.25M System Gates
- Up to 496 I/Os
- Up to 414Kb Embedded Memory
- sysHSI^TM SERDES for 850Mbps Serial

ORCA4 - Up to 900K FPGA System Gates 
Programmable Logic Cell (PLC):
 - Up to 250 Mhz operation (4-levels of LUT)
- 2x4 dual-port memory per block
Programmable Interface Cell (PIC):
- Single-ended: TTL, LVTTL, CMOS, PCI, GTL, GTL+, SSTL3, SSTL2, HSTL, PECL
- Differential: LVDS (including built-in termination resistor), LVPECL
Embedded Block RAMs (EBR): Quad-port RAM (512x18) / ROM / FIFO / Multiplier / CAM
System-Level Design Features:
- 32-/16-/8-bit embedded MicroProcessor Interface (MPI)
- 32-bit multi-master embedded System Bus (ARM AHB bus)
- Up to 8 multi-output PLLs (416 Mhz) with two networking-specific (T1/E1/STS-3/STM-1)

ORCA3 - Up to 340K FPGA System Gates

ORCA2 - Up to 99,400 FPGA system gates

ispXPLD / CPLDs - eXtended Programmable Logic Devices 

ispXPLD - The ispXPLD^TM 5000MX family represents a new class of devices from Lattice Semiconductor called eXpanded Programmable Logic Devices (XPLDs). These devices are built around a new building block, the Multi-Function Block (MFB). These blocks can be individually configured as SuperWIDE^TM (136-input) logic, single- or dual-port memory, FIFO, or CAM

ispMACH4000 - This family includes 3.3V, 2.5V-and 1.8V versions. Densities range from 32 to 512 macrocells

ispMACH4000Z - This family provides the low static power consumption (Standby Current Icc as low as 10µA), cost-effective logic implementation, flexible I/Os and power supply range

ispLSI / ispMACH5000 - With 68 inputs available to each Logic Block, the ispLSI / ispMACH 5000 devices can easily implement complex logic functions, including 64-bit applications, in a single level of logic.

SPLDs - Simple PLDs, 8 to 26 Macrocells in 28 pin packages or smaller

ispGAL - in-system programmable version of the popular 22V10

GAL - 8 to 26 Macrocell Devices

Digital Interconnects 
Generic Digital Crosspoint (GDX) devices represent a class of high-density programmable component, distinct from complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). Each successive family built on the previous concepts: starting from initial GDX family to latest high speed Switching and interfacing ispGDX2 family. Digital Crosspoint devices are available to support 5.0V, 3.3V, 2.5V and 1.8V designs and have been optimized for fast, cost-effective integration of complex interface logic and signal routing applications.

ispGDX2 - consists of devices with up to 16 high speed (850 MHz) SERDES, up to four 330MHz sysCLOCK PLLs, sysIO interface capability and is available in 64, 128 and 256 I/Os. With blazing fast 3.0ns input-to-output speeds and versatile sysIO buffers, the ispGDX2 family supports the most demanding interfacing and interconnect needs of next-generation system designs.

ispGDXV - family consists of devices with 80, 160 and 240 I/Os

ispGDX - The original 5V Family is available in 80, 120 and 160 I/O versions

Analog and Mixed Signal Devices

Lattice introduced the industry's first high-performance in-system programmable analog ICs, ispPAC devices, and fast, easy-to-use PC-based PAC-Designer software: together, these products give you a powerful new approach to design, integrate and configure your analog circuits. Whether in the development lab or in your product in the field, the functions, characteristics and features of these devices can be reconfigured and reprogrammed in seconds, getting products to market faster and extending their features and lifetime. 

Lattice's In-System Programmable Analog methodology radically simplifies and accelerates analog circuit implementation. PC-based PAC-Designer tools provide a simple Windows-based graphical user interface for easy design entry using time-saving analog libraries and circuit-generator macros. Built-in performance verification tools give quick, up-front design feedback before a single device is programmed.

ispPAC Power Manager - Programmable analog inputs support highly accurate, simultaneous monitoring of multiple power supply nodes (up to 12), while an on-chip ruggedized CPLD offers the most efficient mechanism to generate control signals for power supply sequencing and supervisory signal generation

ispPAC - Analog electronics front end that dynamically adapts to its inputs and an implement high performance continuous-time filters from 5th order down to 1st order. 

Software Development Tools

ispLEVER - provides complete support for Lattice CPLD and FPGA design. ispLEVER Base includes Synthesis and Timing Simulation Tools (ModelSim) from Mentor Graphics, and CPLD Synthesis support from Synplicity.

PAC Designer - provides complete support for ispPAC devices and ispPAC Power Manager

Development Hardware

ISP Programming Kits
Download Cables
Socket Adapters
ispPAC Development and Evaluation Boards
FPSC Evaluation Boards